Remember AMD HBCC? Radeon Vega 64 High-Bandwidth Cache Test (Microsoft Flight Simulator 2020)
122FS 2020 - Radeon Vega 64 HBCC Test
1440p ultra (low vol lightning & AO)
Ryzen 9 3900X
16GB DDR4-3200
HBCC is the controller for AMD’s high-bandwidth cache, what the company has functionally renamed from VRAM. There is no hard threshold as to what governs the naming designation of “high-bandwidth cache,” and should AMD produce a hypothetic GDDR5 Vega GPU, its framebuffer would also be named “high-bandwidth cache.” The card does not need HBM to have its framebuffer designated as HBC, in other words.
AMD’s High-Bandwidth Cache Controller is disabled by default. When enabled, the controller effectively converts VRAM into a last-level cache equivalent, then reserves a user-designated amount of system memory for allocation to the GPU. If the applications page-out of the on-card 8GB of HBM2, a trade-off between latency and capacity occurs and the GPU taps-in to system memory to grab its needed pages. If you’re storing 4K textures in HBM2 and exceed that 8GB capacity, and maybe need another 1GB for other assets, those items can be pushed to system memory and pulled via the PCIe bus. This is less effective than increasing on-card memory, but is significantly cheaper than doing so – even in spite of DDR pricing. Latency is introduced by means of traveling across the PCIe interface, through the CPU, and down the memory bus, then back, but it’s still faster than having to dump memory and swap data locally.
Hypothetically, this technology would permit large, working datasets to exist on system memory and give the GPU’s memory controller somewhat direct access to that dataset. Although it’s worse for latency, technically speaking, the additional capacity should outweigh that latency deficit in certain scenarios. It’s just going to take proper implementation to ever realize the gains, and that implementation must happen at both the software developers and AMD.
Microsoft Flight Simulator 2020
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