Leveraging Fine-Grained Multithreading for Efficient SIMD Control Flow

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Recent advances in graphics processing units (GPUs) have resulted in massively parallel hardware that is easily programmable and widely available in commodity desktop computer systems. GPUs typically use single-instruction, multiple-data (SIMD) pipelines to achieve high performance with minimal area overhead. Scalar threads are grouped together into SIMD batches (sometimes referred to as warps). While SIMD is ideally suited for simple programs, recent GPUs include control flow instructions in the GPU instruction set architecture and applications(in particular, general



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