Duration: 58:26

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Modern technology presents chip designers with challenges that will fundamentally alter how processors work and how we design all aspects of computer systems.  The first portion of my talk presents a dataflow-style processor architecture, WaveScalar, that is simpler to design, more scalable, and, in many cases, better performing than conventional processors.  WaveScalar provides a unique hybrid memory interface that supports programs written in imperative languages (C, C++, Java, etc.) and allows programmers to explicitly express memory parallelism.  WaveScalar also provides a flexible multi-granular threading facility and allows programmers to mix thread granularities and memory interface styles  in a single program to express parallelism where it is available.   A WaveScalar processor provides a substrate of simple processing tiles, a hierarchical on-chip network, and a high-bandwidth memory system.  I will present data demonstrating that scaling the size of a WaveScalar design by a factor of 10 results in a commensurate 10-fold increase in performance and that WaveScalar designs outperform conventional chip-multiprocessor designs in both raw performance and area-efficiency.  The second part of the talk builds on my experience designing WaveScalar to explore the larger question of how architectures should affect (and be affected by) programming languages, software engineering practices, and overall system architecture.