Electronics: Why does my PMOS FET not behave correctly when the Drain is at a lower potential the...

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Why does my PMOS FET not behave correctly when the Drain is at a lower potential then the Source? (LTSPICE sim shown)
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(electronics.stackexchange.com/users/485062/arachne)Arachne
(electronics.stackexchange.com/users/117898/ryuji)Ryuji
(electronics.stackexchange.com/users/485062/arachne)Arachne
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batteries ltspice fet latching pmos



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