Intel® ISA-L Erasure Coding | Intel Software

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Published on September 1, 2017 2:17:59 AM ● Video Link: https://www.youtube.com/watch?v=zHetfWe70-0

Duration: 2:47

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As applications have scaled to the datacenter, so have demands on the storage infrastructure that support them. Storage availability and fault tolerance have become a crucial challenge. To ensure storage systems meet datacenter availability requirements, two techniques are pervasive: multi-replication (typically triple-replication) and Reed-Solomon erasure codes (RS EC), both of which ensure there are always copies of the data available despite single or dual failures. Triple replication has the advantage of simplicity, but requires that a system’s raw storage capacity is (at least) 3X the design capacity. By contrast, RS EC has historically been computationally intensive, but is far more flexible and space efficient, enabling raw capacity to be only 1.5X the design capacity. For storage applications requiring large data sets, this difference in the underlying availability algorithm can translate into huge differences in capital and operating expenditures. The Intel® Intelligent Storage Library (Intel ISA-L) includes support for erasure coding. This video describes how the use of erasure coding can benefit a storage application and explains the Intel ISA-L implementation, which uses Reed Solomon error correction (RS EC).

Intel® Intelligent Storage Acceleration Library (Intel® ISA-L): http://intel.ly/2wngTMB

Code sample - Intel® ISA-L Erasure Code and Recovery: http://intel.ly/2wmPQRx

Intel® ISA-L on Github: https://github.com/01org/isa-l?utm_source=ISTV&utm_medium=Video&utm_campaign=ISTV_2017

and: https://github.com/01org/isa-l_crypto?utm_source=ISTV&utm_medium=Video&utm_campaign=ISTV_2017


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