Intel® ISA-L Erasure Coding Sample Application Overview | Intel Software
12Reed-Solomon erasure coding (RS-EC) schemes are well known and have been in use for a long time. This video provides an overview of a code sample that shows how the Intel® Intelligent Storage Library (Intel ISA-L) implementation of RS-EC can keep up with current storage hardware throughput requirements in software rather than offloading to dedicated hardware. To demonstrate, the example creates up to 24 different buffers in memory to store data; a larger data set of up to 256 MB of data is distributed across these buffers. To simulate failure, up to two memory buffers are made inaccessible and the program demonstrates that on Intel® architecture the data can be completely and correctly recovered from the remaining buffers. The example shows one way to incorporate the Intel ISA-L RS-EC feature into your storage applications, and shows how to prepare and recover data.
Intel® Intelligent Storage Acceleration Library (Intel® ISA-L): http://intel.ly/2wngTMB
Code sample - Intel® ISA-L Erasure Code and Recovery: http://intel.ly/2wmPQRx
Intel® ISA-L on Github: https://github.com/01org/isa-l?utm_source=ISTV&utm_medium=Video&utm_campaign=ISTV_2017
and: https://github.com/01org/isa-l_crypto?utm_source=ISTV&utm_medium=Video&utm_campaign=ISTV_2017
Intel® ISA-L on 01.org: http://bit.ly/2wmNzpC
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Intel® ISA-L Erasure Coding Sample Application Overview | Intel Software
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