Duration: 50:28

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Prof. Renau will present the research effort by his team at University of California, Santa Cruz. The talk focuses in Live ASIC/FPGA flows to improve the productivity of hardware design, and if time permits a very brief introduction to a new hardware description language designed at UCSC but still not released outside. The Live ASIC/FPGA flow projects aim at generating from verilog code to GDS or bitstream generation in few seconds. The few seconds goal is to have a productive environment matching the human short-term memory. We aim at generating correct results, not approximate models.The talk will show results using a Xilinx vivado flow capable of performing incremental synthesis, placement, and routing in under 30 seconds without quality loss. Synthesis, placement, and routing turnaround times are some of the major bottlenecks in digital design productivity. Engineers usually wait several hours to get accurate results to design changes that are often quite small. The Live ASIC/FPGA flow is accurate and equivalent to the current flows. This improvement can be achieved only because of the focus on incremental synthesis.

A recent DAC publication, explains one of the first steps with Live Synthesis. The new approach has relatively quick feedback after small, incremental changes. Still not published, but we are working in fast incremental placement and routing for FPGAs and ASICs.

We recently (IWLS17) propose a benchmark (Anubis) for incremental synthesis based on real designs and real design changes. We evaluate Anubis using two incremental commercial flows to give insights on its usage and reporting. If time permits, a short introduction to Pyrope language syntax would be part of the talk.

See more at https://www.microsoft.com/en-us/research/video/livehardware-development-at-ucsc/