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The circuit diagram (see figure) shows a 'logic combination' with the states outputs \( X, Y \) and \( Z \)
\( \mathrm{P} \) given for inputs \( P, Q, R \) and \( S \) all at state 1 (i.e., high). When inputs \( \mathrm{P} \) and \( \mathrm{R} \) change to state 0 (i.e. low) with inputs \( Q \) and \( \mathrm{S} \) still at 1 , the condition of output \( X, Y \) and \( Z \) changes to:
\begin{tabular}{|c|c|c|c|c|}
\hline & \( (1) \) & \( (2) \) & \( (3) \) & \( (4) \) \\
\hline \( \mathrm{X} \) & 1 & 1 & 0 & 0 \\
\hline \( \mathrm{Y} \) & 0 & 1 & 1 & 0 \\
\hline \( \mathrm{Z} \) & 0 & 1 & 0 & 1 \\
\hline
\end{tabular}
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