Stepping through a VCS kernel.
8This demonstration, run through the Stella debugger, shows the drawing of an individual frame of an Atari VCS (2600) game.
The Atari VCS video chip (the TIA, aka Stella), only has enough logic to handle one line of video output, at a time, so the microprocessor has to take the job of loading each line into the TIA at the correct time as the electron beam of the TV sweeps to a given point...actually, just before.
So it is critical, that the code be properly timed. You have one saving grace, the WSYNC register, which causes the processor to wait until the next scanline, and resume execution. This provides a little wall of sanity so you at least know that you're on the beginning of a line.
The TIA divides each horizontal line into 228 individual "clocks", 68 of them which are placed before the start of a visible line (in a space called the Horizontal Blank).
The microprocessor, takes the TIA's clock, and divides it by 3 to produce its master instruction clock. This means, that you actually have 76 processor cycles that happen on a line, 21 of which happen before the visible part of the line begins, in the Horizontal Blank.
Since each tiny instruction takes on average 3-6 cycles, you don't have very many instructions before things start drawing, and you don't have very many instructions that you can do, if you intend to change the way things are drawn in the middle of the screen...you have to be aware of the execution time of each instruction (shown in the code window on the bottom right, as the numbers after each instruction).
Hopefully this gives a bit of insight as to the engineering required to display single frame of video on the VCS. Keep in mind, this is continuously happening, at approximately 60 frames per second (assuming 262 horizontal lines are output, including the non-visible vertical blank and overscan periods, which are used for game logic)